The present invention relates to calibrating Analog-to-Digital Converters (ADCs) or Digital-to-Analog Converters (DACs), especially those which use Charge Coupled Device (CCD) pipeline structures and successive approximation techniques.
Many modern electronic systems require conversion of signals from analog to digital or from digital to analog form. Circuits for performing these functions are now required in numerous common consumer devices such as digital cameras, cellular telephones, wireless data network equipment, audio devices such as MP3 players, and video equipment such as Digital Video Disk (DVD) players, High Definition Digital Television (HDTV) equipment, and numerous other products.
U.S. Pat. No. 4,375,059 issued to Schlig is an early example of a Charge Coupled Device (CCD) based converter. In that design, a number of charge storage stages are arranged as a serial pipeline register so that an input source charges pass from stage to stage down the pipeline. A reference charge generator and a charge splitter at each stage generate reference signals. A first of the reference signals is compared to a source charge that is temporarily stored at the stage. The comparison generates a binary one if the source charge is greater than or equal to the first reference charge, or a binary zero if this source charge is less than the first reference charge. If a binary one is generated, only the stored contents of the stage need pass through to the next successive stage. However, if a binary zero is generated, the stored contents of the stage are passed to a next successive stage, together with a second reference charge, in such a way that the stored charges are combined. Auxiliary buffer registers are provided to temporarily store the output bits of the comparators. This allows forming a digital word for each source charge packet as the packet and its associated charge components travel down the pipeline.
A further refinement in charge to digital converter design is found in U.S. Pat. No. 5,579,007 issued to Paul. In that arrangement, the pipeline produces a serial stream of both positive and negative signal charges corresponding to a differential signal. The differential signal structure provides improved sensitivity in the charge to voltage translation process, and thus increased dynamic range. The structure also exhibits reduce sensitivity to mismatches, by suppression of common mode noise signals in the charge domain.
In order to provide a high precision converter, the differential type successive approximation pipeline must often be trimmed or calibrated. The precision of the calibration apparatus must therefore be considerably better than the converter itself, making its design quite challenging.
Existing converter calibration techniques typically set the converter to a static state and then adjust one or more parameters of the pipeline to provide for Direct Current (DC) balance. These techniques usually require precise, low noise, low DC-offset amplifiers and/or comparators. Unfortunately, thermal noise and low frequency (1/f) noise can cause voltage offsets, which in turn often limit how accurately the converter can be calibrated.